As Complementary Metal Oxide Semiconductor (CMOS) devices have gotten progressively smaller, power supply voltages have been correspondingly reduced to reduce the deleterious effects of voltage differentials across increasingly smaller device dimensions. However, this reduction, from a nominal 5 volts to 3.3 volts has not occurred simultaneously with all manufacturers. Nor has this reduction occurred in all semiconductor devices with which other semiconductor devices must communicate. Thus, a Very Large Scale Integrated (VLSI) chip designed to operate at 3.3 volts may need to interface with another chip operating at 5 volts.
To perform the interface properly requires special circuit or device techniques to avoid stress on components designed for 3.3 volts operation. The alternative is added cost for extra manufacturing steps necessary to make devices which can tolerate higher voltages. Alternative designs also may require greater chip area occupied by buffer circuits.
A typical CMOS receiver stage is simply a ratioed inverter which is designed to work with the prescribed voltage levels (commonly TTL: maximum voltage level for a logic 0 (V.sub.0max) is 0.8 volts; minimum voltage level for a logic 1 (V.sub.1min) is 2.0 volts). Such a typical CMOS receiver is depicted in FIG. 1. However, the maximum input voltage in a standard system is likely to be the 5 volts supply. If 5 volts is applied to the receiver stage of FIG. 1, Q.sub.2 will have gate-to-source and gate-to-drain voltages of 5 volts. For devices designed to operate normally at 3.3 volts, 5 volts across these terminals can result in immediate destruction of the device.
Thus, there remains a need for a CMOS receiver stage that can operate normally with a power supply voltage of 3.3 volts and yet tolerate an input voltage of 5 volts.